Modern microelectronic processors, such as central processing units (CPUs), use embedded cache memory to speed up the performance of the microelectronic processor and/or to meet memory bandwidth requirements, such as with System-on-Chip (SoC) devices. To implement an embedded cache memory with the highest level of integration density, as many bit cells as possible are placed on each bit line, source line and word line of the embedded cache memory. As will be understood to those skilled in the art, the lengths of bit line and word line increase proportionally with the number of bit cells on each. For example, the typical lengths of bit line and word line in an embedded cache memory can be in the order of tens of micrometers in a 22 nm logic process technology. However, the use of long bit lines and word lines may result in the performance of embedded cache memory becoming ever more increasingly sensitive to interconnect resistance, particularly as the size of the embedded cache memory is scaled down and width of the bit lines and word lines reduces. Such resistance may be particularly problematical for resistance-based memory technologies, such as Spin-Transfer Torque (STT) MRAM (Magnetoresistive Random Access Memory) and ReRAM (Resistive Random Access Memory), wherein reducing source line, bit line, and word line resistances with the minimum bit cell area has become one of the top challenges for successful integration of these resistance-based memory technologies. Therefore, there is a need to develop new memory architectures for resistance-based memory to alleviate performance and density limitations caused by high source line and word line resistance and to accommodate limited pitch scaling of the widths of the bit lines and word lines.